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CY7C1379C
9-Mbit (256K x 32) Flow-through SRAM with NoBLTM Architecture
Features
* Can support up to 133-MHz bus operations with zero wait states -- Data is transferred on every clock * Pin compatible and functionally equivalent to ZBTTM devices * Internally self-timed output buffer control to eliminate the need to use OE * Registered inputs for flow-through operation * Byte Write capability * 256K x 32 common I/O architecture * Single 3.3V power supply (VDD) * Fast clock-to-output times -- 6.5 ns (for 133-MHz device) * Clock Enable (CEN) pin to suspend operation * Synchronous self-timed writes * Asynchronous Output Enable * Available in JEDEC-standard lead-free 100-Pin TQFP, lead-free and non lead-free 165-Ball FBGA package * Burst Capability--linear or interleaved burst order * Low standby power
Functional Description[1]
The CY7C1379C is a 3.3V, 256K x 32 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1379C is equipped with the advanced No Bus LatencyTM (NoBLTM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two Byte Write Select (BW[A:D]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.
Logic Block Diagram-CY7C1379C (256K x 36)
A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 Q1 A1' A0' Q0
BURST LOGIC
ADV/LD BWA BWB BWC BWD WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs
OE CE1 CE2 CE3 ZZ
INPUT REGISTER READ LOGIC
E
SLEEP Control
Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05688 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 14, 2006
CY7C1379C
Selection Guide
133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 250 40 100 MHz 7.5 180 40 Unit ns mA mA
Pin Configurations 100-Pin TQFP Pinout
BWB BWA CE1 CE2 CE3 VDD VSS NC(18M) BWD BWC CEN CLK WE OE ADV/LD
A
A 82
A
100
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
BYTE C
BYTE D
NC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC VSS/DNU VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38
81
A
CY7C1379C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
44 45 46 47 48 49 50
NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC
BYTE B
BYTE A
39
40
41
42
A1
A0
NC
NC
43
VSS
A
A
A
VDD
A
A
A
NC(72M)
Document #: 38-05688 Rev. *D
NC(36M)
A
A
A
MODE
A
A
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CY7C1379C
Pin Configurations (continued) 165-Ball FBGA Pinout
CY7C1379C (256K x 32)
1 A B C D E F G H J K L M N P R
NC/576M NC/1G NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC MODE
2
A A NC DQC DQC DQC DQC VDD DQD DQD DQD DQD NC NC/36M
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC
NC
6
CE3 CLK
7
CEN WE
8
ADV/LD OE
9
A NC/18M VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A
11
NC NC NC DQB DQB DQB DQB ZZ DQA DQA DQA DQA NC NC/288M A
A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC NC
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
NC/144M NC/72M
A
A
Pin Definitions
Name A0, A1, A TQFP 37,36,32,33,34,3 5,44,45,46, 47,48,49,50,81,8 2,83,99,100 FBGA R6,P6,A2, A9,A10,B2 B10,P3,P4, P8,P9,P10, R3,R4,R8, R9,R10,R11 B5,A5,A4, B4 B7 I/O Description InputAddress Inputs used to select one of the 256K address Synchronous locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB, BWC, BWD WE
93,94,95,96 88
InputByte Write Inputs, active LOW. Qualified with WE to conduct Synchronous writes to the SRAM. Sampled on the rising edge of CLK. InputWrite Enable Input, active LOW. Sampled on the rising edge Synchronous of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. InputAdvance/Load Input. Used to advance the on-chip address Synchronous counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.
ADV/LD
85
A8
CLK
89
B6
CE1
98
A3
InputChip Enable 1 Input, active LOW. Sampled on the rising edge Synchronous of CLK. Used in conjunction with CE2, and CE3 to select/deselect the device. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge Synchronous of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled on the rising edge Synchronous of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Page 3 of 15
CE2
97
B3
CE3
92
A6
Document #: 38-05688 Rev. *D
CY7C1379C
Pin Definitions (continued)
Name OE TQFP 86 FBGA B8 I/O Description InputOutput Enable, asynchronous input, active LOW. Combined Asynchronous with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. InputClock Enable Input, active LOW. When asserted LOW the Synchronous Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. InputZZ "sleep" Input. This active HIGH input places the device in a Asynchronous non-time critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OBidirectional Data I/O Lines. As inputs, they feed into an Synchronous on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by address during the clock rise of the Read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.
CEN
87
A7
ZZ
64
H11
DQs
52,53,56,57, 58,59,62,63, 68,69,72,73, 74,75,78,79, 2,3,6,7, 8,9,12,13, 18,19,22,23, 24,25,28,29
M11,L11, K11,J11, J10,K10, L10,M10, D10,E10, F10,G10, D11,E11, F11,G11, D1,E1,F1, G1,D2,E2, F2,G2,J1, K1,L1,M1, J2,K2,L2 M2 R1
Mode
31
Input Strap Pin
Mode Input. Selects the burst order of the device. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence.
VDD
15,41,65,91
D4,D8,E4, E8,F4,F8, G4,G8,H2, H4,H8,J4, J8,K4,K8, L4,L8,M4, M8 C3,C9,D3, D9,E3,E9, F3,F9,G3, G9,J3,J9, K3,K9,L3, L9,M3,M9, N3,N9
Power Supply Power supply inputs to the core of the device.
VDDQ
4,11,20,27,54, 61,70,77
I/O Power Supply
Power supply for the I/O circuitry.
Document #: 38-05688 Rev. *D
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CY7C1379C
Pin Definitions (continued)
Name VSS TQFP 5,10,17,21, 26,40,55,60, 67,71,76,90, FBGA C4,C5,C6, C7,C8,D5, D6,D7,E5, E6,E7,F5, F6,F7,G5, G6,G7,H5, H6,H7,J5, J6,J7,K5,K6,K 7,L5,L6,L7,M5 ,M6,M7, N4,N8 I/O Ground Ground for the device. Description
NC
1,16,30,38,39, A1,A11,B1, 42,43,51,66,80,8 B9,B11,C1, 4,95,96 C2,C10,C11,H 1,H3,H9, H10,N1,N2, N5,N6,N7 N10,N11,P1,P 2,P5,P7, P11,R2,R5, R7 14 -
-
No Connects. Not Internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die.
VSS/DNU
Ground/DNU
This pin can be connected to Ground or should be left floating. access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately. Burst Read Accesses The CY7C1379C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs. Page 5 of 15
Functional Overview
The CY7C1379C is a synchronous flow-through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[A:D] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read Document #: 38-05688 Rev. *D
CY7C1379C
On the next clock rise the data presented to DQs (or a subset for Byte Write operations, see Truth Table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BW[A:D] signals. The CY7C1379C provides Byte Write capability that is described in the truth table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1379C is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs and DQPX.are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1379C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW[A:D] inputs must be driven in each cycle of the burst write, in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10
Interleaved Burst Sequence
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to Sleep current ZZ inactive to exit Sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 50 2tCYC Unit mA ns ns ns ns
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CY7C1379C
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation Deselect Cycle Deselect Cycle Deselect Cycle Continue Deselect Cycle READ Cycle (Begin Burst) READ Cycle (Continue Burst) DUMMY READ (Continue Burst) WRITE Cycle (Begin Burst) WRITE Cycle (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) Sleep MODE ADRESS Used CE1 CE2 CE3 ZZ ADV/LD WE None None None None External Next Next External Next None Next Current None H X X X L X L X L X L X X X X X L X H X H X H X H X X X X H X X L X L X L X L X X X L L L L L L L L L L L L L H L L L H L H L H L H L H X X X X X X H X H X L X L X X X BWX OE CEN CLK X X X X X X X X L L H H X X X X X X L L H H X X X X X X L L L L L L L L L L L L H X L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H X DQ Tri-State Tri-State Tri-State Tri-State Data Out (Q) Data Out (Q) Tri-State Tri-State Data In (D) Data In (D) Tri-State Tri-State - Tri-State
NOP/DUMMY READ (Begin Burst) External
Truth Table for Read/Write[2, 3]
Function (CY7C1379C) Read Write No Bytes Written Write Byte A - (DQA) Write Byte B - (DQB) Write Byte C - (DQC) Write Byte D - (DQD) Write All Bytes WE H L L L L L L BWA X H L H H H L BWB X H H L H H L BWC X H H H L H L BWD X H H H H L L
Notes: 2. X ="Don't Care." H = HIGH, L = LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Truth Table for details. 3. Write is defined by BWX, and WE. See Truth Table for Read/Write. 4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs = Three-state when OE is inactive or when the device is deselected, and DQs = data when OE is active.
Document #: 38-05688 Rev. *D
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CY7C1379C
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ...... -0.5V to +VDD DC Voltage Applied to Outputs in High-Z State .................................... -0.5V to VDDQ + 0.5V Range Com'l Ind'l DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Ambient Temperature (TA) 0C to +70C -40C to +85C VDD/VDDQ 3.3V - 5%/+10%
Electrical Characteristics Over the Operating Range [9, 10]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[9] Input Leakage Current except ZZ and MODE Input Current of MODE Input Current of ZZ IOZ IDD ISB1 for 3.3V I/O for 3.3V I/O, IOH = -4.0 mA for 3.3V I/O, IOL = 8.0 mA for 3.3V I/O for 3.3V I/O GND VI VDDQ Input = VSS Input = VDDQ Input = VSS Input = VDDQ Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current Automatic CE Power-down Current--TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz -5 -5 30 5 250 180 110 2.0 -0.3 -5 -30 5 Test Conditions Min. 3.135 3.135 2.4 0.4 VDD + 0.3V 0.8 5 Max. 3.6 VDD Unit V V V V V V A A A A A A mA mA mA
VDD = Max, Device Deselected, All speeds VIN VIH or VIN VIL, f = fMAX, inputs switching
ISB2
Automatic CE VDD = Max, Device Deselected, All speeds Power-down VIN VDD - 0.3V or VIN 0.3V, Current--CMOS Inputs f = 0, inputs static VDD = Max, Device Deselected, All speeds Automatic CE Power-down VIN VDDQ - 0.3V or VIN 0.3V, Current--CMOS Inputs f = fMAX, inputs switching Automatic CE Power-down Current--TTL Inputs VDD = Max, Device Deselected, All speeds VIN VIH or VIN VIL, f = 0, inputs static
40
mA
ISB3
100
mA
ISB4
40
mA
Notes: 9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 10. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05688 Rev. *D
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CY7C1379C
Capacitance[11]
Parameter CIN CCLOCK CI/O Description Input Capacitance Clock Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V VDDQ=3.3V 100 TQFP Max. 5 5 5 165 FBGA Max. 7 7 7 Unit pF pF pF
Thermal Resistance[11]
Parameters JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 100 TQFP Package 29.41 6.13 165 FBGA Package 16.8 3.0 Unit C/W C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 5 pF INCLUDING JIG AND SCOPE R = 351 R = 317 ALL INPUT PULSES VDD 10% GND 1 ns 90% 90% 10% 1 ns
VL = 1.5V
(a)
(b) Range[12, 13, 14, 15, 16, 17] -133
(c)
Switching Characteristics Over the Operating
Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Data Output Valid after CLK Rise Data Output Hold after CLK Rise Clock to Low-Z[15, 16, 17] Clock to High-Z[15, 16, 17] OE LOW to Output Valid Clock Cycle Time Clock HIGH Clock LOW
-100 Min. 1 10.0 4.0 4.0 6.5 7.5 2.0 0 3.5 3.5 3.5 3.5 0 3.5 3.5 Max. Unit ms ns ns ns ns ns ns ns ns ns ns
Description VDD(Typical) to the First Access[14]
Min. 1 7.5 3.0 3.0
Max.
2.0 0
OE LOW to Output Low-Z[15, 16, 17] OE HIGH to Output High-Z[15, 16, 17]
0
Notes: 11. Tested initially and after any design or process changes that may affect these parameters. 12. Timing reference level is 1.5V when VDDQ=3.3V. 13. Test conditions shown in (a) of AC Test Loads, unless otherwise noted. 14. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD (minimum) initially, before a read or write operation can be initiated. 15. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 16. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 17. This parameter is sampled and not 100% tested.
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CY7C1379C
Switching Characteristics Over the Operating Range[12, 13, 14, 15, 16, 17] (continued)
-133 Parameter Set-up Times tAS tALS tWES tCENS tDS tCES Hold Times tAH tALH tWEH tCENH tDH tCEH Address Hold after CLK Rise ADV/LD Hold after CLK Rise WE, BWX Hold after CLK Rise CEN Hold after CLK Rise Data Input Hold after CLK Rise Chip Enable Hold after CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up before CLK Rise ADV/LD Set-up before CLK Rise WE, BW[A:D] Set-up before CLK Rise CEN Set-up before CLK Rise Data Input Set-up before CLK Rise Chip Enable Set-up before CLK Rise 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Description Min. Max. -100 Min. Max. Unit
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CY7C1379C
Switching Waveforms
Read/Write Waveforms[18, 19, 20]
1 CLK
tCENS tCENH
2
tCYC
3
4
5
6
7
8
9
10
tCH
tCL
CEN
tCES tCEH
CE ADV/LD WE BW[A:D] ADDRESS
tAS
A1
tAH
A2
A3
tCDV tCLZ
A4
tDOH Q(A3) Q(A4) tOEHZ tOEV
A5
tCHZ
A6
A7
DQ
tDS
D(A1) tDH
D(A2)
D(A2+1)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
OE COMMAND
WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1)
tOELZ
tDOH
WRITE D(A5)
READ Q(A6)
WRITE D(A7)
DESELECT
DON'T CARE
UNDEFINED
Notes: 18. For this waveform ZZ is tied LOW. 19. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 20. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05688 Rev. *D
Page 11 of 15
CY7C1379C
Switching Waveforms (continued)
NOP, STALL and Deselect Cycles[18, 19, 21]
1 CLK CEN CE ADV/LD WE BW[A:D] ADDRESS DQ COMMAND
WRITE D(A1)
2
3
4
5
6
7
8
9
10
A1
A2 D(A1)
READ Q(A2) STALL
A3 Q(A2)
READ Q(A3)
A4 Q(A3)
WRITE D(A4) STALL
A5
tCHZ
D(A4)
NOP READ Q(A5)
Q(A5)
tDOH DESELECT CONTINUE DESELECT
DON'T CARE
UNDEFINED
ZZ Mode Timing[22, 23]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. 22. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 23. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05688 Rev. *D
Page 12 of 15
CY7C1379C
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1355C-133AXC CY7C1355C-133BZC CY7C1355C-133BZXC CY7C1355C-133AXI CY7C1355C-133BZI CY7C1355C-133BZXI 100 CY7C1355C-100AXC CY7C1355C-100BZC CY7C1355C-100BZXC CY7C1355C-100AXI CY7C1355C-100BZI CY7C1355C-100BZXI Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free 51-85122 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm) 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free 51-85122 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm) 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free 51-85122 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm) 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free 51-85122 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm) 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm) Lead-Free
lndustrial
Commercial
lndustrial
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Document #: 38-05688 Rev. *D
0.10
R 0.08 MIN. 0.20 MAX.
Page 13 of 15
CY7C1379C
Package Diagrams (continued)
165-ball FBGA (13 x 15 x 1.2 mm) (51-85122)
51-85122-*C
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05688 Rev. *D
Page 14 of 15
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1379C
Document History Page
Document Title: CY7C1379C 9-Mbit (256K x 32) Flow-through SRAM with NoBLTM Architecture Document Number: 38-05688 REV. ** *A ECN NO. 286269 320834 Issue Date See ECN See ECN Orig. of Change PCI PCI New data sheet Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added 133 MHz in the Ordering Information table Changed JA and JC for TQFP Package from 25 and 9 C/W to 29.41 and 6.13 C/W respectively Changed JA and JC for FBGA Package from 27 and 6 C/W to 16.8 and 3.0 C/W respectively Modified VOL, VOH test conditions Corrected IDD, tCDV, tCH, tDOH and tCL for 100MHz to 180 mA, 7.5 ns, 4 ns, 2 ns and 4 ns respectively Changed Snooze to Sleep in the ZZ Mode Electrical Characteristics and truth table Added Industrial operating range Added BZC package in the Ordering Information table Updated Ordering Information Table Changed ISB2 from 30 to 40 mA Modified test condition in note# 10 from VDDQ < VDD to VDDQ < VDD Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Changed three-state to tri-state Converted from preliminary to final Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Updated the Ordering Information table. Description of Change
*B *C
377095 408725
See ECN See ECN
PCI RXU
*D
501828
See ECN
VKN
Document #: 38-05688 Rev. *D
Page 15 of 15

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